Bus protocol

ABSTRACT

A write-only data transfer protocol for peripheral component interface busses and a method for transferring data between source and destination communication units is provided. The method includes the source communication unit writing a buffer allocation request to the destination unit and, in response to the buffer allocation request, the destination communication unit allocating space within an associated buffer to receive the data to be sent. The method also includes the destination communication unit writing at least the location of the allocated buffer to the source communication unit and the source communication unit writing the data to be sent to the allocated buffer location.

FIELD OF THE INVENTION

The present invention relates to data transfer protocols generally andto such protocols for implementation on a peripheral component interface(PCI) bus and within a network switch in particular.

BACKGROUND OF THE INVENTION

A network switch creates a network among a plurality of nodes (connectedto personal computers, workstations, etc.) and other network switchesconnected thereto. As shown in FIG. 1 to which reference is now made,each node 10 is connected to one port of a switch 12. Further ports 14also serve to connect network switches together. The switches aretypically connected together via a bus 16. Optionally, a centralprocessing unit (CPU) 15 which is associated with a main memory element17 can also be connected to the bus 16. The CPU 15 overseas thecommunication operations which occur between the network switches 12.The main memory 17 temporarily stores packets of data to be transferredbetween switches 12.

Each node 10 sends packets of data to the network switch 12 which thenroutes the packets either to another of the nodes connected thereto orto a network switch to which the destination node is connected. In thelatter case, the destination network switch then routes the packet tothe destination node.

Each network switch also has to temporarily store the packets of data,in buffers 18, while the switch determines how, when and through whichport to retransmit the packets. Each packet can be transmitted to onlyone destination address (a “unicast” packet) or to more than one unit (a“multicast” or “broadcast” packet). For multicast and broadcast packets,the switch typically stores the packet only once and transmits multiplecopies of the packet to some (multicast) or all (broadcast) of itsports. Once the packet has been transmitted to all of its destinations,it can be removed from its buffer 18 or written over.

One example of a prior art process of transferring packets betweennetwork switches is illustrated in FIGS. 2A and 2B to which reference isadditionally made. FIG. 2A is a block diagram illustration of the flowof data between the source and destination network switches and FIG. 2Bis a timing diagram of the activity of the bus 16.

The source network switch 12A, on its own schedule reads the packet fromits temporary storage location, labeled 19A, and writes the packet tothe main memory 17 (step 20). The source network switch 12A thenprovides (step 22) an indication to the CPU 15 that the transfer hasfinished. At some later point after the transfer has finished, the CPU15 indicates (step 24) to the destination network switch 12B that themain memory 17 is storing its data.

When the destination network switch 12B receives the notification fromthe CPU 15, the destination network switch 12B begins the read processand takes control of the bus 16. The read process includes steps 26-32,as follows. In step 26, the destination network switch 12B determineswhere, in its temporary storage unit there is room for the incomingpacket (for example location 19B). In step 28, destination networkswitch 12B asks the main memory 17 to read the packet and, when thepacket is received, switch 12B places it (step 30) into the availablelocation 19B. When the destination network switch 12B has finished theread operation, it, in step 32, sends a message to the CPU 15 that thepacket was properly received. In step 34, the CPU 15 receives thereceipt message and clears the location in the main memory 17 in whichthe data was previously stored.

FIG. 2B illustrates the timing of the packet transfer. The packettransfer begins with the “source write” (SW) operation of steps 20-22which is generally a short operation. At some later point, thedestination read (DR) operation occurs. Since the read process includesallocating the storage location and accessing the main memory 17, andsince main memory 17 typically reads at a slow rate, the read operationtakes a long time. Unfortunately, during the read operation, no otherswitch can access the bus. Thus, the rate of data transfer is limited bythe speed at which the main memory 17 can read the data, even if the bus16 and the other components can operate at faster speeds.

SUMMARY OF THE PRESENT INVENTION

Applicants have realized that, since read operations are limited by thespeed of the main memory 17 (or of any other memory being read), whilewrite operations occur at the speed of the bus 16, the utilizationefficiency of the bus can be increased if data transfers are performedusing only write operations.

It is therefore an object of the present invention to provide awrite-only bus transfer mechanism in which no read operations occur. Inthe present invention, data is written directly, such as by directmemory transfer, from one network switch to the other and a packet isnot sent from the source network switch until the destination networkswitch has allocated a storage location for the packet and has notifiedthe source network switch of the allocated storage location. Thus, thepacket can immediately be written into the destination network switch assoon as it arrives at the destination network switch. Furthermore, sincethe storage space is allocated for the packet before the packet is eversent, the source network switch does not need to wait for a receivenotice before beginning to send the next packet.

In one embodiment, the method includes the steps of:

-   -   a) the source communication unit writes a buffer allocation        request to the destination unit;    -   b) in response to the buffer allocation request, the destination        communication until allocates space within an associated buffer        to receive the data to be sent;    -   c) the destination communication unit writes at least the        location of the allocated buffer to the source communication        unit; and    -   d) the source communication unit writes the data to be sent to        the allocated buffer location.

Additionally, in accordance with a preferred embodiment of the presentinvention, the step of writing a buffer allocation request includes thestep of writing at least the address of the source communication unitand the size of the data to be transferred into a buffer allocationrequest register of the destination communication unit. Similarly, thesecond step of writing includes the step of writing at least the addressof the allocated buffer and of the destination communication unit into astart of packet register in the source communication unit.

Moreover, in accordance with a preferred embodiment of the presentinvention, the steps of writing are performed by direct memory accesstransfer.

Further, in accordance with a preferred embodiment of the presentinvention, the source and destination communication units are physicallyseparate units.

Finally, in accordance with a preferred embodiment of the presentinvention, the source communication unit can write a) the data to besent on a bus data line and b) at least the address of the destinationcommunication unit and the address of a buffer location within thedestination communication unit on a bus address line.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 is a schematic illustration of two prior art network switchesconnected together by a bus;

FIG. 2A is a flow chart illustration of the operations performed by thetwo switches of FIG. 1 during the prior art data transfer operation;

FIG. 2B is a timing diagram illustration of the activity of the busduring the operation of FIG. 2A;

FIG. 3 is a schematic illustration of two network switches, constructedand operative in accordance with a preferred embodiment of the presentinvention;

FIG. 4A is a flow chart illustration of the operations performed by thetwo switches of FIG. 3 during the data transfer operation of the presentinvention; and

FIG. 4B is a timing diagram illustration of the activity of the busduring the operations of FIG. 4A.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Reference is now made to FIG. 3 which illustrates the networkconfiguration of the present invention and to FIGS. 4A and 4B whichillustrate the data transfer operation of the present invention.Elements of FIG. 3 which are similar to those of FIG. 1 have the samereference numerals. As can be seen in FIG. 3 the present invention doesnot need the CPU 15 or the main memory 17 for the data transferoperation. This is because the present invention provides a “write-only”data transfer operation in which packets of data are written directlyinto the destination network switch 12B. It is noted that, in oneembodiment, the data transfer operations utilized are direct memoryaccess (DMA) write transfers.

The network switches of the present invention additionally have aplurality of registers 21 which are utilized during the data transferoperation. These registers can form part of the storage unit in whichthe buffers 18 are located or they can be separate therefrom.Furthermore, it is noted that the bus 16 has at least two lines, a dataline 40 and an address line 42.

In the present invention, packets of data are not transferred until abuffer location 19 is allocated for them in the buffer 18 of thedestination network switch 12B. Furthermore, since the transferoperation is a DMA transfer, a packet is directly written into thelocation allocated therefor.

The present discussion will consider the transfer of a single packet ofdata. It will be appreciated that many packets of data can betransferred in parallel by performing the operations describedhereinbelow many times either in parallel or serially.

In accordance with a preferred embodiment of the present invention, whena packet of data is to be transferred, the source network switch 12Ainitially writes (step 50, FIG. 4A) a “buffer request” message to theregister 21b of the destination network switch 12B. The buffer requestmessage asks that the destination network switch allocate a buffer forthe data to be transferred.

In the DMA transfer embodiment of the present invention, the sourcenetwork switch 12A provides, on address line 42, the address of the“buffer request” register, the address of destination network switch 12Band its “return” address. Source network switch 12A provides, on dataline 40, the size (or byte count) of the packet to be transferred andthe buffer location 19A in which it is stored. The data of the data lineis then written directly into the buffer request register.

In response to the buffer request message, the destination networkswitch 12B determines (step 52) the buffer location 19B in which thepacket can be stored. It then writes (step 54) a “start of packet”message to the register 21a of the source network switch 12A whichincludes at least the location of the allocated buffer and the portnumbers of the source and destination network switches. It can alsoinclude the byte count.

For example, in the DMA transfer embodiment of the present inventiondescribed hereinabove, the destination network switch 12B provides, onaddress line 42, the address of the “start of packet” register and theaddress of source network switch 12A. Destination network switch 12Bprovides, on data line 40, at least the following: the byte count of thepacket to be transferred, the address 19B of the allocated buffer, theport number of the destination network switch 12B, and, foridentification, the buffer location 19A in which the data is stored inthe source network switch 12A and the port number of the source networkswitch 12A. As before, the data of the data line is then directlywritten into the start of packet register.

In response to receipt of the start of packet message in the start ofpacket register, the source network switch 12A writes (step 56) thepacket of data to the allocated buffer location, followed by an “end ofpacket” message. Once the source network switch 12A has finished writingthe end of packet message, it is free to send the next packet, beginningat step 50.

In the above described embodiment, the writing of the packet of datainvolves providing the address of the destination network switch 12B andthe buffer location 19B on the address line 42 and the packet to betransferred on the data line 40. The transferred packet is then directlywritten into the allocated buffer location 19B. The end of packetmessage is written in a similar manner to the other messages. Theaddress information includes the address of the end of packet registerand the address of the destination network switch 12B. The data includesthe port number of the destination network switch 12B, the bufferlocation 19B and the byte count.

When the packet arrives at the destination network switch 12B itdirectly writes (step 60) the packet into the allocated buffer location19B, as per the address on the address line 42, until it receives theend of packet message for that allocated buffer location. Thedestination network switch 12B is now free to perform other operationsuntil it receives a next buffer allocation request.

FIG. 4B illustrates the timing of the packet transfer described in FIG.4A. The initial source write operation of the buffer request message(step 50) is typically relatively short since write operations takerelatively little time and since the message to be transferred is small.Some time later, there is a destination write (DW) operation of thestart of packet message (step 54). The destination write operation takesapproximately the same length of time as the first source writeoperation. Some time later, there is a further source write operation(step 56) of the packet transfer and end of packet message. Since, forthis operation, there is more data to be transferred, this source writeoperation is shown to take a longer time than the other two writeoperations.

A comparison of the timing of FIGS. 2B and 4B indicate that the amountof time the bus is utilized for a single transfer operation is muchsmaller in the present invention (FIG. 4B) than in the prior art (FIG.2B) since the present invention utilizes write operations only.

The source and network switches are free to perform other operationsafter they finish their writing operations.

It is also noted that, in the present invention, the source networkswitch 12A is free to operate on other packets once it has finishedwriting its packet, and its associated end of packet message, to thebus. The source network switch 12A does not need to ensure that thedestination network switch 12B has successfully received the packetsince, in the present invention, the address for the data (in thedestination network switch) is known and is fully allocated prior tosending the packet; the packet would not be sent if there was no bufferlocation available for it. In the present invention, the time it takesfor the destination network switch 12B to process the packet is notrelevant to the operation of the source network switch 12A.

It will be appreciated that the data transfer mechanism describedhereinabove can be implemented in any type of network switch or othercommunication device communicating along a bus, such as transferringdata to a peripheral hard disk. For example, it can be implemented in anEthernet switch, an asynchronous transfer mode (ATM) switch or a TokenRing switch. The present invention is may be implemented for peripheralcomponent interface (PCI) busses or for any other bus.

It will further be appreciated by persons skilled in the art that thepresent invention is not limited to what has been particularly shown anddescribed hereinabove. Rather the scope of the present invention isdefined by the claims which follow:

1. A method for transferring data between source and destinationcommunication units, the method comprising the steps of: a. the sourcecommunication unit writing a buffer allocation request to thedestination communication unit; b. in response to the buffer allocationrequest, the destination communication unit allocating space within anassociated buffer to receive the data to be sent; c. the destinationcommunication unit writing at least the location of the allocated bufferto the source communication unit; and d. the source communication unitwriting the data to be sent to the allocated buffer location.
 2. Amethod according to claim 1 and wherein said step of writing a bufferallocation request includes the step of writing at least the address ofsaid source communication unit and the size of the data to betransferred into a buffer allocation request register of saiddestination communication unit.
 3. A method according to claim 1 andwherein said second step of writing includes the step of writing atleast the address of the allocated buffer and of the destinationcommunication unit into a start of packet register in said sourcecommunication unit.
 4. A method according to claim 3 and wherein saidsecond step of writing includes further comprising the step of: thedestination communication unit writing at least thean address of theanallocated buffer and of the destination communication unit into a startof packet register in said source communication unit.
 5. A methodaccording to claim 1 and wherein said source and destinationcommunication units are physically separate units.
 6. A method accordingto claim 1 wherein said steps of writing are performed by direct memoryaccess transfer.
 7. A method for transferring data between source anddestination communication units, the method comprising the steps of: a.the source communication unit writing the data to be sent with anindication of the buffer location into which the destinationcommunication unit should write the data to be sent.
 8. A methodaccording to claim 7 wherein said step of writing is performed by directmemory access transfer.
 9. A method for transferring data between sourceand destination communication units connected via a bus having a dataline and an address line, the method comprising the steps of: a. thesource communication unit writing the data to be sent on said data lineand at least the address of said destination communication unit and theaddress of a buffer location within said destination communication uniton said address line.
 10. A method according to claim 9 wherein saidstep of writing is performed by direct memory access transfer.
 11. Awrite-only data transfer protocol for peripheral component interfacebusses for transferring data between source and destination peripheralcomponents, the method comprising the steps of: a. the source peripheralcomponent writing a buffer allocation request to the destination unitperipheral component; b. in response to the buffer allocation request,the destination nation peripheral component allocating space within anassociated buffer to receive the data to be sent; c. the destinationperipheral component writing at least the location of the allocatedbuffer to the source peripheral component; and d. the source peripheralcomponent writing the data to be sent to the allocated buffer location.12. A method according to claim 11 wherein said steps of writing areperformed by direct memory access transfer.
 13. A communications systemcomprising: a source communication unit comprising a source buffer; adestination communication unit in communication with said sourcecommunication unit, and comprising a destination buffer; wherein, inresponse to a destination buffer allocation request by said sourcecommunication unit to said destination communication unit, saiddestination communication unit (i) allocates a location within saiddestination buffer to receive the data to be sent from said sourcecommunication unit, and (ii) provides at least the location of saiddestination buffer to said source communication unit, and wherein saidsource communication unit provides the data to said destination bufferfor storage at the location.
 14. A communication system according toclaim 13, wherein said source communication unit further comprises afirst switching unit responsive to a first plurality of source nodes,and wherein said destination communication unit further comprises asecond switching unit in communication with a second plurality ofdestination nodes.
 15. A communication system according to claim 14,further comprising an address line and a data line, wherein thedestination buffer allocation request by said source communication unitto said destination communication unit is provided on said address line,wherein said destination communication unit provides the location ofsaid destination buffer to said source communication unit on saidaddress line, and wherein said source communication unit provides thedata to said destination buffer on said data line.
 16. A communicationsystem according to claim 15, wherein said destination communicationunit provides (i) a start of the location of said destination buffer tosaid source communication unit on said address line, and (ii) and anaddress of said source communication unit on the data line.
 17. Acommunication system according to claim 15, wherein said sourcecommunication unit further comprises a source register, and wherein thedestination buffer allocation request by said source communication unitto said destination communication unit comprises (i) an address of saidsource register, (ii) an address of said second switching unit, and(iii) an address of said first switching unit.
 18. A communicationsystem according to claim 15, wherein said source communication unitfurther comprises a source register, and wherein the destination bufferallocation request by said source communication unit to said destinationcommunication unit comprises (i) a size of the data to be transferredand (i) an address of said source buffer storing the data.
 19. Acommunication system according to claim 18, wherein, in response to adestination buffer allocation request by said source communication unitto said destination communication unit, said destination communicationunit further provides the location of said destination buffer and anaddress of said source communication unit to a start of packet registerin said source register.
 20. A communication system according to claim15, wherein, in response to a destination buffer allocation request bysaid source communication unit to said destination communication unit,said destination communication unit further provides the location ofsaid destination buffer and an address of said source communication unitto said source communication unit on said address line.
 21. Acommunication system according to claim 13, wherein said destinationcommunication unit further comprises a destination register, and whereinthe destination buffer allocation request by said source communicationunit to said destination communication unit is provided to saiddestination register.
 22. A communication system according to claim 13,wherein, in response to a destination buffer allocation request by saidsource communication unit to said destination communication unit, saiddestination communication unit further provides the location of saiddestination buffer and an address of said source communication unit tosaid source communication unit.
 23. A communication system comprising: asource node; a source communication unit in communication with saidsource node and comprising a source buffer; a destination communicationunit in communication with said source communication unit and comprisinga destination buffer, wherein, in response to a destination bufferallocation request by said source communication unit to said destinationcommunication unit, said destination communication unit (i) allocates alocation within said destination buffer to receive the data to be sentfrom said source communication unit, and (ii) provides at least thelocation of said destination buffer to said source communication unit,and wherein said source communication unit provides the data to saiddestination buffer for storage at the location; and a destination nodein communication with said destination communication unit.
 24. Acommunication system according to claim 23, wherein said sourcecommunication unit further comprises a first switching unit responsiveto a first plurality of source nodes, and wherein said destinationcommunication unit further comprises a second switching unit incommunication with a second plurality of destination nodes.
 25. Acommunication system according to claim 24, further comprising anaddress line and a data line, wherein the destination buffer allocationrequest by said source communication unit to said destinationcommunication unit is provided on said address line, wherein saiddestination communication unit provides the location of said destinationbuffer to said source communication unit on said address line, andwherein said source communication unit provides the data to saiddestination buffer on said data line.
 26. A communication systemaccording to claim 25, wherein said destination communication unitprovides (i) a start of the location of said destination buffer to saidsource communication unit on said address line, and (ii) an address ofsaid source communication unit on said data line.
 27. A communicationsystem according to claim 25, wherein said source communication unitfurther comprises a source register, wherein the destination bufferallocation request by said source communication unit to said destinationcommunication unit comprises (i) an address of said source register,(ii) an address of said second switching unit, and (iii) an address ofsaid first switching unit.
 28. A communication system according to claim27, wherein, in response to a destination buffer allocation request bysaid source communication unit to said destination communication unit,said destination communication unit further provides the location ofsaid destination buffer and an address of said source communication unitto a start of packet register in said source register.
 29. Acommunication system according to claim 25, wherein said sourcecommunication unit further comprises a source register, and wherein thedestination buffer allocation request by said source communication unitto said destination communication unit comprises a size of the data tobe transferred and an address of said source buffer storing the data.30. A communication system according to claim 25, wherein, in responseto a destination buffer allocation request by said source communicationunit to said destination communication unit, said destinationcommunication unit further provides the location of said destinationbuffer and an address of said source communication unit to said sourcecommunication unit on said address line.
 31. A communication systemaccording to claim 23, wherein said destination communication unitfurther comprises a destination register, and wherein the destinationbuffer allocation request by said source communication unit to saiddestination communication unit is provided to said destination register.32. A communication system according to claim 23, wherein, in responseto a destination buffer allocation request by said source communicationunit to said destination communication unit, said destinationcommunication unit further provides the location of said destinationbuffer and an address of said source communication unit to said sourcecommunication unit.
 33. A communications system comprising: sourcecommunication means for transmitting and receiving data comprisingsource buffer means for storing data; destination communication meansfor transmitting and receiving data in communication with said sourcecommunication means and comprising destination buffer means for storingdata; wherein, in response to a destination buffer means allocationrequest by said source communication means to said destinationcommunication means, said destination communication means (i) allocatesa location within said destination buffer means to receive the data tobe sent from said source communication means, and (ii) provides at leastthe location of said destination buffer means to said sourcecommunication means, and wherein said source communication meansprovides the data to said destination buffer means for storage at thelocation.
 34. A communication system according to claim 33, wherein saidsource communication means further comprises first switching means forrouting data responsive to a first plurality of source nodes, andwherein said destination communication means further comprises secondswitching means for routing data in communication with a secondplurality of destination nodes.
 35. A communication system according toclaim 34, further comprising an address line means for transferring dataand a data line means for transferring data, wherein the destinationbuffer means allocation request by said source communication means tosaid destination communication means is provided on said address linemeans, wherein said destination communication means provides thelocation of said destination buffer means to said source communicationmeans on said address line means, and wherein said source communicationmeans provides the data to said destination buffer means on said dataline means.
 36. A communication system according to claim 35, whereinsaid destination communication means provides (i) a start of thelocation of said destination buffer means to said source communicationmeans on said address line means and (ii) an address of said sourcecommunication means on said data line means.
 37. A communication systemaccording to claim 35, wherein said source communication means furthercomprises source register means for storing data, wherein thedestination buffer means allocation request by said source communicationmeans to said destination communication means comprises (i) an addressof said source register means, (ii) an address of said second switchingmeans, and (iii) an address of said first switching means on saidaddress line means.
 38. A communication system according to claim 37,wherein, in response to a destination buffer means allocation request bysaid source communication means to said destination communication means,said destination communication means further provides the location ofsaid destination buffer means and an address of said sourcecommunication means to a start of packet register means in said sourceregister means.
 39. A communication system according to claim 35,wherein said source communication means further comprises sourceregister means for storing data, wherein the destination buffer meansallocation request by said source communication means to saiddestination communication means comprises a size of the data to betransferred and an address of said source buffer means storing the dataon said data line means.
 40. A communication system according to claim35, wherein, in response to a destination buffer means allocationrequest by said source communication means to said destinationcommunication means, said destination communication means furtherprovides the location of said destination buffer means and an address ofsaid source communication means to said source communication means. 41.A communication system according to claim 33, wherein in response to adestination buffer means allocation request by said source communicationmeans to said destination communication means; said destinationcommunication means further provides the location of said destinationbuffer means and an address of said source communication means to saidsource communication means.
 42. A communication system according toclaim 33, wherein said destination communication means further comprisesdestination register means for storing data, and wherein the destinationbuffer means allocation request by said source communication means tosaid destination communication means is provided to said destinationregister means.
 43. A communication system comprising: source node meansfor sourcing data; source communication means in communication with saidsource node means comprising source buffer means for storing data;destination communication means in communication with said sourcecommunication means and comprising destination buffer means for storingdata, wherein, in response to a destination buffer means allocationrequest by said source communication means to said destinationcommunication means, said destination communication means (i) allocatesa location within said destination buffer means to receive the data tobe sent from said source communication means, and (ii) provides at leastthe location of said destination buffer means to said sourcecommunication means, and wherein said source communication meansprovides the data to said destination buffer means for storage at thelocation; and destination node means for sinking data in communicationwith said destination communication means.
 44. A communication systemaccording to claim 43, wherein said source communication means furthercomprises first switching means for routing data responsive to a firstplurality of source node means, and wherein said destinationcommunication means further comprises second switching means for routingdata in communication with a second plurality of destination node means.45. A communication system according to claim 44, further comprising anaddress line means for transferring data and a data line means fortransferring data, wherein the destination buffer means allocationrequest by said source communication means to said destinationcommunication means is provided on said address line means, wherein saiddestination communication means provides the location of saiddestination buffer means to said source communication means on saidaddress line means, and wherein said source communication means providesthe data to said destination buffer means on said data line means.
 46. Acommunication system according to claim 45, wherein said destinationcommunication means provides (i) a start of the location of saiddestination buffer means to said source communication means on saidaddress line means and (ii) an address of said source communicationmeans on said data line means.
 47. A communication system according toclaim 45, wherein said source communication means further comprisessource register means for storing data, wherein the destination buffermeans allocation request by said source communication means to saiddestination communication means comprises (i) an address of said sourceregister means, (ii) an address of said second switching means, and(iii) an address of said first switching means on said address linemeans.
 48. A communication system according to claim 47, wherein, inresponse to a destination buffer means allocation request by said sourcecommunication means to said destination communication means, saiddestination communication means further provides the location of saiddestination buffer means and an address of said source communicationmeans to a start of packet register means in said source register means.49. A communication system according to claim 45, wherein said sourcecommunication means further comprises source register means for storingdata, and wherein the destination buffer means allocation request bysaid source communication means to said destination communication meanscomprises a size of the data to be transferred and an address of saidsource buffer means storing the data on said data line means.
 50. Acommunication system according to claim 45, wherein, in response to adestination buffer means allocation request by said source communicationmeans to said destination communication means, said destinationcommunication means further provides the location of said destinationbuffer means and an address of said source communication means to saidsource communication means on said address line means.
 51. Acommunication system according to claim 43, wherein, in response to adestination buffer means allocation request by said source communicationmeans to said destination communication means, said destinationcommunication means further provides the location of said destinationbuffer means and an address of said source communication means to saidsource communication means.
 52. A communication system according toclaim 43, wherein said destination communication means further comprisesdestination register means for storing data, and wherein the destinationbuffer means allocation request by said source communication means tosaid destination communication means is provided to said destinationregister means.